FPGA & ASIC - Electronic Design Verification and Simulation Software for SystemC, VHDL, Verilog, SystemVerilog, Assertions, EDIF, MATLAB/Simulink
http://www.aldec.com/Technologies/Technology.aspx?technologyid=bce19256-b8a1-4b49-97e6-f756654c65cc

Support for VHDL, Verilog, EDIF, SystemC, SystemVerilog, SVA, OVA, and PSL languages ... The interface included in Riviera enables users to execute MATLAB commands, call M ...
http://www.mathworks.com/products/connections/product_main.html?prod_id=716&prod_name=Riviera

The RTAX EDIF Netlist Converter compliments the hardware adaptor by allowing for a ... In-Hardware Simulation; DO-254 Compliance; MATLAB/Simulink Co-Simulation; Verification IP; HDL ...
http://www.aldec.com/Technologies/Technology.aspx?technologyid=bce19256-b8a1-4b49-97e6-f756654c65cc&print=1

FPGA & ASIC - Electronic Design Verification and Simulation Software for VHDL, VERILOG, SYSTEM VERILOG, SYSTEM C, EDIF, Matlab/Simulink
http://support.aldec.com/knowledgebase/Article.aspx?aid=000262

FPGA & ASIC - Electronic Design Verification and Simulation Software for VHDL, VERILOG, SYSTEM VERILOG, SYSTEM C, EDIF, Matlab/Simulink
http://support.aldec.com/knowledgebase/Article.aspx?aid=000743&show=vsa00198.htm

The Agility products include unique software technologies for MATLAB® to C software ... DK Design Suite produces Xilinx device data directly to Xilinx EDIF, integrated into ...
http://www.xilinx.com/products/design_tools/logic_design/advanced/esl/agility.htm

Matlab, R14 SP3 ; Simulink ; Communications Blockset ; Communications Toolbox ; Control System ... Scholar (schematic capture, EDIF-capable) SmartSpice (simulation) Verilog-A (behavioral ...
http://CUPERTINOSIGNAL.NET

... capabilities as well as 'Handel-C'-to-RTL and direct synthesis of 'Handel-C'-to-EDIF for ... Faster execution of MATLAB algorithms' Agility RMS (Rapid Matlab Simulator) converts Matlab ...
http://www.msc.rl.ac.uk/europractice/software/agility.html

Begin icmake Performing step: bcc Executing: bcc -t edif -u 0 -s de -o mychip.edif -L /tools/sshaft/lib/icmake/mdl/R11 -L matlab -c mychip matlab/tut1.mdl >& log ...
http://bwrc.eecs.berkeley.edu/Research/IC_Design_Flow/Flow/assembly/tut/tut1/default.html

... JScript, PeopleSoft SQR, Ada 83, MIPS, BANN, Delphi, Python, Euphoria, Bash shell script, CSS, SQL, ASP, PHP, JSP, EDIF, VHDL, Verilog-HDL, HTML, C/C++, Perl, Java, Matlab ...
http://crimsoneditor.com/.

... the 32-bit integer representation of the logarithm. LNS ALU C-code Implementation for Matlab ... by the Handel-C tools and the XILINX Alliance 2.1i tools to place and route from the EDIF ...
http://dsp.vscht.cz/konference_matlab/matlab00/hermanek.pdf

... standards and interfaces with popular EDA products such as Synopsys® SmartModels?, Novas?, Denali®, MATLAB®, and Simulink®. HDL Language Support: VHDL, Verilog®, EDIF ...
http://icjournal.com/news/2008/06/20060609_10.htm

This editor allows you to edit different text-based files such as programming languages including HTML, C/C++, Perl, Java, Matlab, LaTeX, ASP, PHP, JSP, EDIF, VHF and Verilog-HDL.
http://www.tucows.com/preview/195771

... Hardware/software partitioning and architectural exploration; Cycle-accurate C simulation environment; Co-simulation of C models with MATLAB, RTL models; Optimized EDIF output to FPGA ...
http://www.mil-embedded.com/products/search/?q=Celoxica%2C+Inc.&cd=deadmatch&max=80

ChannelCore64 is supplied as an EDIF netlist, and includes a VHDL model and test bench, and a bit-true Matlab model. The standard core is designed for use with Xilinx Virtex II ...
http://www.rfel.com/products/Products_ChannelCore64.asp

Mixed VHDL, Verilog, SystemC, SystemVerilog, and EDIF simulation; SLP accelerated ... FPGA and ASIC designs has a built-in interface to the intuitive, technical computing MATLAB ...
http://www.mathworks.com/products/connections/product_main.html?prod_id=525&prod_name=Active-HDL

GUI Matlab program that drives the Xilinx ISE backend tools to synthesize the VHDL ... Synthesis Only: synthesize the design to either NGC (XST) or EDIF file (Synplify ...
http://bwrc.eecs.berkeley.edu/Research/BEE/BEE1/doc/designflow/bee_ise.htm

Verilog/VHDL source code or verilog EDIF netlist. Extensive testing environment (test bench + stimuli generator). Matlab model.
http://turbobest.com/tb_ldpc80211n.htm

... to either RTL (VHDL or Verilog, preserving signal names) or directly to an EDIF ... They can also co-simulate VHDL, Verilog, SystemC, and Handel C as well as Matlab models
http://www.deepchip.com/items/dac04-04.html

Verilog source code or verilog EDIF netlist. Verilog testing environment. Matlab model. Documentation.
http://turbobest.com/tb_ctc_dec10.htm